Fourth International Workshop

OMHI

On-chip memory hierarchies and interconnects:
                             organization, management and implementation


August 2015, Vienna, Austria

to be held in conjunction with Euro-Par 2015

 

program

09:00-09:15 Welcome and Opening Remarks

09:15-10:30 Keynote
Sandro Bartolini, University of Siena, Italy.
Sandro Bartolini graduated in "Computer Engineering" at the Università di Pisa, Italy, where he got his PhD in "Computer Science and Engineering" in 2003. Since 2002 he is a full-time researcher at the Department of Information Engineering and Mathematical Sciences at the University of Siena, where he leads a computer architecture research group. His main research interests comprise: computer architecture, high-performance Chip Multi Processors (CMPs) enabled by on-chip photonics, optical and hybrid electro-optical NoCs, feedback-driven compiler optimizations for cache hierarchy (embedded and high-performance) and low power (embedded systems), performance evaluation and tracing, special-purpose accelerators for embedded and high-performance systems, new approaches to productive programmability of heterogeneous architectures (CPU-like and GPU-like). In the last years he has been active in identifying promising approaches to leverage integrated photonics strengths in serving the specific requirements of near future tiled chip multiprocessors for both consumption and performance improvements. He followed a strong cross-layer approach for serving computer-architecture specific requirements: parallel execution, directory-based coherence, shared-memory and hybrid electro-optical NoCs. He is member of IEEE and ACM, and associate editor of Eurasip Journal of Embedded Computing. He is an active member of the HiPEAC European Network of Excellence since 2004. He has co-organized 8 editions of the MeDEA Workshop (with IEEE/ACM PACT conference). He has been co-guest editor of Transactions on High PErformance Architectures and Compilation (HIPEAC III) journal (Springer, 2011), Journal of Embedded Computing, ACM SigArch Computer Architecture Newsletter.

Illuminating processors: how photonics will help computing
Nowadays and foreseen on-chip networking issues for chip-multiprocessors (CMPs) are posing serious challenges to their scalability and power sustainability as core count will further increase. Silicon photonics is emerging as a technological breakthrough that can deliver promising raw features like low-latency, power almost independent of distance and bandwidth scalability. However, to translate this potential into actual performance and consumption improvements, careful design need to be performed, adopting an unprecedented multi-layer approach, encompassing integrated decisions from some very low-level technological choices, through network-level choices and up to higher-level computer-architecture effects reaching the memory hierarchy management and even possible software-related optimizations. Furthermore, different domains, e.g. high-performance, HPC or embedded, can require specific approaches and benefit from different trade-offs. The talk will summarize the current industrial situation, expected roadmaps and main technological challenges towards the adoption of integrated photonics into mainstream products. Then it will discuss some specific research cases, design points and results into the domain of future chip multiprocessors taking advantage of with silicon photonics interconnections.

10:30-11:00 Coffee break

11:00-12:30 Paper Session 1
Chair Julio Sahuquillo

Efficient DVFS Operation in NoCs through a Proper Congestion Management Strategy
José V. Escamilla, José Flich and Pedro J. García

Superoptimizing Memory Subsystems for Multiple Objectives
Joseph Wingbermuehle, Ron Cytron and Roger Chamberlain




Paper Submission: June 2, 2015

Paper Notification: June 30, 2015

Early Registration: July 17, 2015

Workshop Date: August 24, 2015

Camera-Ready: October 2, 2015





Submit your paper here.

Accepted papers presented at the workshop have been published in Lecture Notes in Computer Science (LNCS), volume 9523. You can find it online.

A best paper award will be given to the paper (or papers) presented at the workshop as judged by the Program Chair in collaboration with the Program Committee.




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