Second International Workshop


On-chip memory hierarchies and interconnects:
                             organization, management and implementation

August 2013, Aachen, Germany

to be held in conjunction with Euro-Par 2013


Paper Submission (extended):
June 10, 2013

Paper Notification: July 8, 2013

Camery-ready:  July 26, 2013

Workshop Date: August 27, 2013

Accepted papers presented at the workshop have been published in Lecture Notes in Computer Science (LNCS), volume 8374. You can find information about it here.

A best paper award will be given to the paper (or papers) presented at the workshop as judged by the Program Chair in collaboration with the Program Committee.

The Second International Workshop on On-chip memory hierarchies and interconnects: organization, management and implementation (OMHI2013) will be held in Aachen, Germany. This workshop is organized in conjunction with the Euro-Par annual series of international conferences dedicated to the promotion and advancement of all aspects of parallel computing.


about the workshop




Performance of current chip multiprocessors (CMPs) is mainly dominated by the data access latencies. To alleviate this problem, current CMPs include high amounts of on-chip memory storage, organized either as caches or main memory. Cores fetch the requested data by traversing an on-chip interconnects. Latencies are mainly affected by the devised on-chip memory hierarchy and the interconnect design, whose latencies can dramatically grow with the number of cores. This problem aggravates as the number of cores increases. Thus, new cache hierarchies and interconnects organizations are required to address this problem.

These on-chip cache hierarchies have been typically built employing Static Random Access Memory (SRAM) technology, which is the fastest existing electronic memory technology. This technology presents important design challenges in terms of density and high leakage currents, so that it is unlikely the implementation of future cache hierarchies with only SRAM technology, especially in the context of chip multiprocessors (CMPs).  Instead, alternative technologies (e.g. eDRAM or MRAM) addressing leakage and density are being explored in large CMPs.  This fact enables the design of alternative on-chip hierarchies. Finally, to take advantage of these complex hierarchies, efficient management is required. This includes, among others, thread allocation policies, cache management strategies, and the NoC design, both in 2D and 3D designs.

This workshop will provide a forum for engineers and scientists to address challenges, and to present new ideas for on-chip memory hierarchies and interconnects focusing on organization, management and implementation.

Authors are invited to submit high quality papers representing original work in (but not limited to) the following topics:

  1. On-chip memory hierarchy organizations: homogeneous and heterogeneous technologies, including persistent memories.

  2. On-chip memory management: prefetching, replacement algorithms, data replication and promotion.

  3. Thread allocation to cores, scheduling, workload balancing and programming.

  4. Cache hierarchy/coherence protocol/network co-design.

  5. Power and energy management.

  6. Tradeoffs among performance, energy and area.

  7. Moving data among on-chip and off-chip memories.